Integrated circuit memory devices are widely used in consumer and commercial applications. More specifically, conventional read/write memory devices such as Dynamic Random Access Memory (DRAM) devices are often used as part of a data processing system that includes a Central Processing Unit (CPU). It may be difficult to operate a conventional DRAM at speeds that are compatible with the overall system speed.
In order to allow a DRAM to operate at high speed, "synchronous" DRAMs, also referred to as SDRAMs, have been developed. A synchronous DRAM can receive a system clock that is synchronous with the processing speed of the overall system. The internal circuitry of the SDRAM can be operated in such a manner as to accomplish read/write operations in synchronism with the system clock. Thus, for example, in an SDRAM, a row active signal and a read/write command may be input in synchronization with the system clock. SDRAMs are described in U.S. Pat. No. 5,610,874 to Park et al. entitled "Fast Burst-Mode Synchronous Random Access Memory Device"; U.S. Pat. No. 5,384,750 to Lee entitled "Data Output Buffer of a Synchronous Semiconductor Memory Device"; U.S. Pat. No. 5,555,526 to Kim entitled "Synchronous Semiconductor Memory Device Having an Auto-Precharge Function"; and U.S. Pat. No. 5,568,445 to Park et al. entitled "Synchronous Semiconductor Memory Device With a Write Latency Control Function", assigned to the assignee of the present application, the disclosures of which are hereby incorporated herein by reference.
It is also known to use a data input/output mask (DQM) signal that is applied from external to the integrated circuit, in order to mask output data from the memory device during a read operation and to mask input data to the memory device during a write operation. More specifically, if the DQM signal is applied when the output data is generated by an output driver during a read operation, the read DQM latency may be equal to 2. Accordingly, the second generated output data from the time the DQM signal is applied, is masked. On the other hand, the write DQM latency may be equal to 0 during the write operation, to prevent the enabling of a column select line corresponding to an address to which the DQM signal is applied. Accordingly, the writing of data to the corresponding memory cell is masked. An SDRAM generally includes a data input/output masking pin (DQM pin) for masking undesired data when a data read/write command is generated, as described above.
SDRAMs include Single Data Rate (SDR) SDRAMs and Double Data Rate (DDR) SDRAMs. In an SDR SDRAM, data can be input and output at either only the rising edge or only the falling edge of a clock signal. In a DDR SDRAM, data can be input and output at both the rising and falling edges of the clock signal. Therefore, the DDR SDRAM can have a data bandwidth which is twice the clock frequency.
FIG. 1 is a timing diagram showing a data masking method of an SDR SDRAM according to conventional technology. Referring to FIG. 1, the data DQ, the command CMD, and the data masking signal DQM are synchronized to the rising edge of a clock CLK. The masking latency for reading the data DQ is 2. The masking latency for writing the data DQ is 0.
Therefore, when the command CMD for writing the data DQ is applied, the data DQ is masked when the data masking signal DQM is activated to logic high, i.e., first input data (DIN1). When the command CMD for reading the data DQ is applied, the data DQ is masked after two periods of the clock CLK, i.e., first output data DOUT1 after the data masking signal DQM is activated to logic high. In FIG. 1, the first input data DIN1 and the first output data DOUT1 are marked with diagonal shading in the data DQ.
In an integrated circuit memory device, the input and output of the data are performed under the control of a set of integrated circuit devices, referred to as a "chipset". In the data read command, data can be masked in the chipset without masking the data in the DRAM since the data is transmitted from the DRAM to the CPU. However, in the data write command, the data which is not desired to be written is generally masked in the DRAM since the data is transmitted from the CPU to DRAM. Therefore, in the data write command, the data is generally masked in the DRAM. In the data read command, the data need not necessarily be masked in the DRAM.
In a DDR SDRAM, the data is sampled at the rising and the falling edges of the clock and all the commands excluding the data are sampled at the rising edge of the clock. Thus, when the data masking signal is activated to logic high during the "1" period of the clock, two successive data are masked. The sampling window of the data is therefore reduced to half that of the SDR synchronous DRAM. Therefore, the data may need to be fetched quickly.
In order to solve the above problem, a data strobe signal for fetching the input and output data is used. The data may be input and output by synchronizing the data with the data strobe signal.
FIG. 2 is a timing diagram showing a method for masking the data of a DDR SDRAM according to conventional technology. Referring to FIG. 2, the data masking signal DQM is synchronized at the rising edge of the clock CLK. The data DQ is not synchronized with the clock CLK and is synchronized at the rising and falling edges of the data strobe signal DS for fetching the data DQ. Therefore, two successive data units of the data DQ are written during one period of the data strobe signal DS.
The data masking signal DQM is synchronized at the rising edge of the clock CLK and is divided into a first data masking signal DQM.sub.-- EVEN for masking even data DQ and a second data masking signal DQM.sub.-- ODD for masking odd data DQ.
The data masked by the first data masking signal DQM.sub.-- EVEN and the second data masking signal DQM.sub.-- ODD are marked with diagonal shading in FIG. 2.
However, since the data masking signals double in the above method, the number of pins to which the data masking signals are input may also double. Accordingly, the number of pins of the chipset may increase. For example, a current PC chipset includes eight data masking pins to which the data masking signal is input. When the data masking pins are increased to sixteen in an SDRAM package, the data masking pins of the chipset may also need to be increased to sixteen.